`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/06/24 21:08:00
// Design Name: 
// Module Name: Top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Top (
    input  [0:0] clk,
    input  [0:0] rst,
    input  [0:0] step,
    input  [7:0] In,
    output [7:0] Data,

    output [6:0] a_to_g_0,
    output [6:0] a_to_g_1,
    output [7:0] an 

    
);

    reg [0:0] clkt = 0;

    wire [0:0] Output_Top_Flag;
    wire [31:0]datas;
    reg [31:0]data_reg = 32'b0;

    
    reg [23:0] count = 24'b0;
    wire [0:0] divclk;
    always @(posedge clk) begin
        count = count +1'b1;
    end

    assign divclk = count[23:23];


    always @(posedge clk) begin
        if(datas != 32'b0)begin
            data_reg = datas;
        end
        else if(rst == 1) begin
            data_reg = 32'b0;
        end
    end





                 
    assign Data = data_reg[7:0];

    RiscV u_RiscV (
        .clk(divclk),
        .rst(rst[0:0]),
        .Input_Top({In}),
        .Output_Top(datas),
        .Output_Top_Flag(Output_Top_Flag)
    );



    Hex_7_Seg_Top I_Hex_7_Seg_Top(
        .num(data_reg),
        .clk(clk),
        .rst(rst),
        .a_to_g_0(a_to_g_0),
        .a_to_g_1(a_to_g_1),
        .an(an)

    );



endmodule
